GAL16V8Z
GAL16V8ZD
Zero Power E
2
CMOS PLD
Features
• ZERO POWER E
2
CMOS TECHNOLOGY
— 100
µ
A Standby Current
— Input Transition Detection on GAL16V8Z
— Dedicated Power-down Pin on GAL16V8ZD
— Input and Output Latching During Power Down
• HIGH PERFORMANCE E
2
CMOS TECHNOLOGY
— 12 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
— 8 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Output Drive
— UltraMOS
®
Advanced CMOS Technology
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Architecturally Similar to Standard GAL16V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Battery Powered Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
8
I
OLMC
OE
Functional Block Diagram
I/CLK
CLK
8
I
8
I
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 32)
8
OLMC
I/O/Q
I/DPP
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I/O/Q
I/OE
Description
The GAL16V8Z and GAL16V8ZD, at 100
µA
standby current and
12ns propagation delay provides the highest speed and lowest
DESCRIPTION
power combination PLD available in the market. The GAL16V8Z/
ZD is manufactured using Lattice Semiconductor's advanced zero
power E
2
CMOS process, which combines CMOS with Electrically
Erasable (E
2
) floating gate technology.
The GAL16V8Z uses Input Transition Detection (ITD) to put the
device in standby mode and is capable of emulating the full func-
tionality of the standard GAL16V8. The GAL16V8ZD utilizes a
dedicated power-down pin (DPP) to put the device in standby mode.
It has 15 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
DIP/SOIC
PLCC
I/CLK
Vcc
I/O/Q
I/C LK
I
I
1
2
3
4
5
6
7
8
9
10
20
19
Vcc
I/ O/ Q
I/ O/ Q
I/ O/ Q
I/ O/ Q
I/ O/ Q
I
3
I/DPP
I
I
I
I
6
4
I
1
19
18
I/O/Q
I/O/Q
16
I/O/Q
I/O/Q
GAL
18
GAL16V8Z
GAL16V8ZD
Top View
9
I
GND
I/D P P
I
I
16V8Z
17
16V8ZD
16
15
14
13
12
11
I
I
I
GND
I/O/Q
I/O/Q
I/ O/ Q
I /O E
8
11
I/OE
I/O/Q
14
13
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
16v8zzd_03
1
LATTICE [ LATTICE SEMICONDUCTOR ]
