GAL16V8D-20LR/833 参数 Datasheet PDF下载

GAL16V8/883

High Performance E

2

CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E

2

CMOS

®

TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 100 MHz

— 6 ns Maximum from Clock Input to Data Output

— TTL Compatible 12 mA Outputs

— UltraMOS

®

Advanced CMOS Technology

• 50% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc

• ACTIVE PULL-UPS ON ALL PINS (GAL16V8D-7 and

GAL16V8D-10)

• E CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 20-pin PAL

®

Devices with Full Function/

Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I

8

I

OLMC

OE

Functional Block Diagram

I/CLK

CLK

8

I

8

I

OLMC

I/O/Q

OLMC

I/O/Q

PROGRAMMABLE

AND-ARRAY

(64 X 32)

8

OLMC

I/O/Q

2

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I/O/Q

I/OE

Description

The GAL16V8/883 is a high performance E

2

CMOS program-

mable logic device processed in full compliance to MIL-STD-883.

This military grade device combines a high performance CMOS

process with Electrically Erasable (E

2

) floating gate technology to

provide the highest speed/power performance available in the

883 qualified PLD market. The GAL16V8D/883, at 7.5ns maxi-

mum propagation delay time, is the world's fastest military quali-

fied CMOS PLD.

The generic GAL architecture provides maximum design flexibil-

ity by allowing the Output Logic Macrocell (OLMC) to be config-

ured by the user. The GAL16V8/883 is capable of emulating all

standard 20-pin PAL

®

devices with full function/fuse map/para-

metric compatibility.

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. Therefore,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write

cycles and data retention in excess of 20 years are specified.

Pin Configuration

CERDIP

LCC

I/CLK

I

I

3

I

I

I

I

I

8

9

I

GND

11

I/OE I/O/Q

13

I/O/Q

6

4

I

2

I/CLK Vcc

20

I/O/Q

19

18

I/O/Q

I/O/Q

1

20

Vcc

I/O/Q

I/O/Q

I

I

I

I

I

5

GAL

16V8

15

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

GAL16V8

Top View

16

I/O/Q

I/O/Q

14

I/O/Q

I

I

GND

10

11

I/OE

Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

February 1999

16v8mil_03

1