Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-5. General Purpose PLL (GPLL) Diagram
Dynamic Adjustment
Dynamic Delay Adjustment
LOCK
CLKI
Input Clock
Divider
CLKOS
(CLKI)
(from routing or external pin)
Voltage
Controlled
Oscillator
Post Scalar
Phase/Duty
Divider
(CLKOP)
Delay
Adjust
Select
Feedback
Divider
CLKFB
CLKOP
CLKOK
(CLKFB)
from CLKOP (PLL internal),
from clock net(CLKOP) or from
a user clock (pin or logic)
RST
Secondary
Divider
RSTK
(CLKOK)
PLLCAP External Pin
(Optional External Capacitor)
Standard PLL (SPLL)
Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but
without delay adjustment capability. SPLLs also provide different parametric specifications. For more information,
please see the list of additional technical documentation at the end of this data sheet.
Table 2-4 provides a description of the signals in the GPLL and SPLL blocks.
Table 2-4. GPLL and SPLL Blocks Signal Descriptions
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
CLKFB
I
RST
I
I
“1” to reset PLL counters, VCO, charge pumps and M-dividers
“1” to reset K-divider
RSTK
CLKOS
O
O
O
O
I
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (no phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
CLKOP
CLKOK
LOCK
DDAMODE1
DDAIZR1
DDAILAG1
DDAIDEL[2:0]1
DPA MODES
DPHASE [3:0]
DDDUTY [3:0]
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
Dynamic Delay Input
I
I
I
I
DPA (Dynamic Phase Adjust/Duty Cycle Select) mode
DPA Phase Adjust inputs
I
—
DPA Duty Cycle Select inputs
1. These signals are not available in SPLL.
2-7
LATTICE [ LATTICE SEMICONDUCTOR ]
