Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Figure 2-10. Primary Clock Sources for ECP2-50
Clock Input
Clock Input
From Routing
PLL Input
PLL Input
SPLL
SPLL
CLK
DIV
CLK
DIV
Clock
Clock
Input
Input
Primary Clock Sources
to Eight Quadrant Clock Selection
Clock
Clock
Input
Input
DLL Input
PLL Input
DLL Input
PLL Input
DLL
DLL
GPLL
GPLL
From Routing
Clock Input
Clock Input
Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device
have six SPLLs.
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