DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 3-17. Reference Clock
Symbol
Description
Test Conditions
Min.
—
Typ.
100
0.65
—
Max.
—
Units
MHz
V
F
Reference clock frequency
Input common mode voltage
Clock input rise/fall time
Differential input voltage swing
Input clock duty cycle
REFCLK
V
—
—
CM
T /T
—
1.0
1.6
60
ns
R
F
V
0.6
40
—
V
SW
DC
50
%
REFCLK
PPM
Reference clock tolerance
-300
—
+300
ppm
3-43