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ECP2-35 参数 Datasheet PDF下载

ECP2-35图片预览
型号: ECP2-35
PDF下载: 下载PDF文件 查看货源
内容描述: LatticeECP2 / M系列数据表 [LatticeECP2/M Family Data Sheet]
分类和应用:
文件页数/大小: 386 页 / 2475 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Architecture  
LatticeECP2/M Family Data Sheet  
Lattice Semiconductor  
MULTADDSUBSUM sysDSP Element  
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-  
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/  
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction  
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows  
the MULTADDSUBSUM sysDSP element.  
Figure 2-26. MULTADDSUBSUM  
Shift Register B In  
Multiplicand A0  
Shift Register A In  
m
m
CLK (CLK0,CLK1,CLK2,CLK3)  
CE (CE0,CE1,CE2,CE3)  
m
n
Multiplier B0  
n
Multiplier  
Input Data  
Register A  
m
n
RST(RST0,RST1,RST2,RST3)  
m+n  
(default)  
n
x
Input Data  
Register B  
Pipeline  
Register  
m
Add/Sub0  
n
Multiplicand A1  
Multiplier B1  
m
m+n  
(default)  
m
n
Multiplier  
Input Data  
Register A  
n
n
m+n+1  
n
x
Input Data  
Register B  
SUM  
Pipeline  
Register  
Output  
Multiplicand A2  
Multiplier B2  
m
m
m
m+n+2  
m+n+2  
n
n
Multiplier  
m
n
Input Data  
Register A  
m+n  
(default)  
n
x
m+n+1  
Input Data  
Register B  
Pipeline  
Register  
m
Add/Sub1  
n
Multiplicand A3  
Multiplier B3  
m
m+n  
(default)  
m
n
Multiplier  
Input Data  
Register A  
m
n
n
x
Input Data  
Register B  
Pipeline  
Register  
m
n
Signed A  
Signed B  
Input  
Register  
Pipeline  
Register  
To Add/Sub0, Add/Sub1  
To Add/Sub0, Add/Sub1  
Input  
Register  
Pipeline  
Register  
Addn0  
Addn1  
Input  
Register  
Pipeline  
Register  
To Add/Sub0  
To Add/Sub1  
Input  
Register  
Pipeline  
Register  
Shift Register B Out  
Shift Register A Out  
Clock, Clock Enable and Reset Resources  
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset  
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)  
2-26  
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