Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.)
LFE2-20
LFE2-35
208
256
484
672
484
672
Pin Type
Bank0
PQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
0
0
0
0
0
0
0
0
0
0
0
0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
0
1
2
2
2
3
0
0
0
2
0
2
Available DDR-Interfaces per I/O
Bank1
0
2
3
3
3
3
0
1
3
4
3
4
0
1
2
3
1
3
0
1
2
2
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCI Capable I/Os per Bank
19
18
0
32
17
0
46
46
0
50
68
0
46
46
0
54
68
0
0
0
0
0
0
0
0
0
0
0
0
0
1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1
DQSB + 8 DQs + 1 DM + Bank VREF1).
4-8
LATTICE [ LATTICE SEMICONDUCTOR ]
