Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.)
LFE2-70E/SE
Ball Number
K28
Ball/Pad Function
PR25A
PR24B
PR24A
GNDIO2
PR23B
PR23A
PR22B
PR22A
VCCIO2
PR21B
PR21A
PR20B
GNDIO2
PR20A
PR19B
PR19A
PR18B
VCCIO2
PR18A
PR15B
GNDIO2
PR15A
PR14B
PR14A
VCCIO2
GNDIO2
PR6B
Bank
2
2
2
-
Dual Function
RDQ29
Differential
T (LVDS)*
J24
RDQ21
C
T
J26
RDQ21
GND
K29
2
2
2
2
99
2
2
2
-
RDQ21
RDQ21
RDQ21
RDQ21
C (LVDS)*
K30
T (LVDS)*
J23
C
T
J25
VCCIO
J27
RDQ21
RDQS21
RDQ21
C (LVDS)*
T (LVDS)*
C
J28
H26
GND
H24
2
2
2
2
2
2
2
-
RDQ21
RDQ21
RDQ21
RDQ21
T
J29
C (LVDS)*
T (LVDS)*
C
J30
H25
VCCIO
H23
RDQ21
T
G27
GND
H27
RUM1_SPLLC_FB_A/RDQ12
C
2
2
2
2
-
RUM1_SPLLT_FB_A/RDQ12
RUM1_SPLLC_IN_A/RDQ12
RUM1_SPLLT_IN_A/RDQ12
T
G29
G28
VCCIO
GND
G26
G25
G30
F30
C (LVDS)*
T (LVDS)*
2
2
2
2
2
2
2
2
-
C (LVDS)*
PR6A
T (LVDS)*
PR5B
C
T
PR5A
VCCIO
F26
VCCIO2
PR4B
C (LVDS)*
T (LVDS)*
C
F27
PR4A
F29
PR3B
GND
F28
GNDIO2
PR3A
2
2
2
2
1
1
-
T
H29
PR2B
VREF2_2
VREF1_2
C (LVDS)*
T (LVDS)*
H30
PR2A
VCCIO
B26
VCCIO2
PT100B
PT100A
GNDIO1
PT99B
VREF2_1
VREF1_1
C
T
A26
GND
C25
1
C
4-121
LATTICE [ LATTICE SEMICONDUCTOR ]
