Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA
LFE2-12E/12SE
LFE2-20E/20SE
Ball
Number
Ball/Pad
Function
Ball/Pad
Function
Bank
Dual Function
Differential
Bank
Dual Function
Differential
L8
M10
M11
M12
M13
M15
M8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N10
N11
N12
N13
N15
N8
P14
P20
P3
P9
R10
R11
R12
R13
U17
U6
W2
W21
Y14
Y9
H6
J6
NC
NC
H3
NC
NC
H2
NC
NC
H17
H16
H20
H18
K6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
J16
N18
N6
NC
NC
VCC
VCC
VCC
VCC
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-59
LATTICE [ LATTICE SEMICONDUCTOR ]
