Specifications ispGDX240VA
Architecture
The ispGDXVA architecture is different from traditional The various I/O pin sets are also shown in the block
PLD architectures, in keeping with its unique application diagram below. The A, B, C, and D I/O pins are grouped
focus. The block diagram is shown below. The program- together with one group per side.
mable interconnect consists of a single Global Routing
I/O Architecture
Pool (GRP). Unlike ispLSI devices, there are no pro-
grammable logic arrays on the device. Control signals for
OEs, Clocks/Clock Enables and MUX Controls must
come from designated sets of I/O pins. The polarity of
these signals can be independently programmed in each
I/O cell.
Each I/O cell contains a 4:1 dynamic MUX controlled by
two select lines as well as a 4x4 crossbar switch con-
trolledbysoftwareforincreasedroutingflexiability(Figure
1). The four data inputs to the MUX (called M0, M1, M2,
and M3) come from I/O signals in the GRP and/or
adjacent I/O cells. Each MUX data input can access one
quarter of the total I/Os. For example, in a 240-I/O
ispGDXVA, each data input can connect to one of 60 I/O
pins. MUX0 and MUX1 can be driven by designated I/O
pins called MUXsel1 and MUXsel2. Each MUXsel input
covers25%ofthetotalI/Opins(e.g.60outof240).MUX0
andMUX1canbedrivenfromeitherMUXsel1orMUXsel2.
Each I/O cell drives a unique pin. The OE control for each
I/O pin is independent and may be driven via the GRP by
one of the designated I/O pins (I/O-OE set). The I/O-OE
set consists of 25% of the total I/O pins. Boundary Scan
test is supported by dedicated registers at each I/O pin.
In-system programming is accomplished through the
standard Boundary Scan protocol.
Figure 1. ispGDXVA I/O Cell and GRP Detail (240 I/O Device)
Logic “1”
Logic “0”
240 I/O Inputs
I/O Cell 239
I/O Cell 238
I/OCell 0
I/O Cell 1
•
•
•
E2CMOS
Programmable
Interconnect
Prog.
Bus Hold
Latch
Prog.
To 2 Adjacent
I/O Cells above
From MUX Outputs
Pull-up
Bypass Option
of 2 Adjacent I/O Cells
(VCCIO)
N+2
N-1
4-to-1 MUX
M0
M1
M2
Register
or Latch
N+1
4x4
I/O Group A
I/O Group B
I/O Group C
I/O Group D
I/O
Pin
C
R
A
B
Crossbar
Switch
D
Q
M3
CLK
N-2
Prog. Open Drain
MUX0 MUX1
•
•
•
•
•
•
CLK_EN Reset
From MUX Outputs
of 2 Adjacent I/O Cells
To 2 Adjacent
I/O Cells below
2.5V/3.3V Output
Prog. Slew Rate
Boundary
Scan Cell
I/O Cell N
•
•
•
I/O Cell 118
I/O Cell 121
I/O Cell 120
• • • • • •
I/O Cell 119
120 I/O Cells
120 I/O Cells
240 Input GRP
Inputs Vertical
Outputs Horizontal
Global
Reset
Y0-Y3
Global
Clocks /
ispGDXVA architecture enhancements over ispGDX (5V)
Clock_Enables
3
LATTICE [ LATTICE SEMICONDUCTOR ]
