Specifications
ispLSI 2192VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.
A
A
A
–
–
–
A
–
–
A
–
A
–
B
C
B
C
–
–
3
1
#
1
2
3
4
5
6
7
8
9
DESCRIPTION
-225
–
–
225
1
tsu2 + tco1
-180
–
–
180
5.0
7.5
–
–
–
–
MIN. MAX. MIN. MAX.
4.0
6.2
–
–
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
2
Clock Frequency with External Feedback
(
)
150
250
2.5
–
3.2
–
–
–
–
0.0
–
–
–
–
–
–
2.0
2.0
3.5
0.0
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.7
6.0
6.0
6.0
4.5
4.5
–
–
3.5
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
5
USE 2032VE-2
25 FOR
NEW DESIGNS
125
200
3.5
–
3.5
–
–
–
0.0
–
–
–
–
–
–
2.5
2.5
4.5
0.0
4.5
7.0
–
4.0
10.0
10.0
5.0
5.0
–
–
PRELIMINARY
Table 2-0030A/2192VE
LATTICE [ LATTICE SEMICONDUCTOR ]
