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2128VE 参数 Datasheet PDF下载

2128VE图片预览
型号: 2128VE
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V在系统可编程SuperFAST⑩高密度PLD [3.3V In-System Programmable SuperFAST⑩ High Density PLD]
分类和应用:
文件页数/大小: 19 页 / 235 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI 2128VE  
Signal Descriptions  
Signal Name  
Description  
RESET  
Active Low (0) Reset pin resets all the registers in the device.  
Global Output Enable input pins.  
GOE 0, GOE1  
Y0, Y1, Y2  
Dedicated Clock Input These clock inputs are connected to one of the clock inputs of all the GLBs in  
the device.  
BSCAN  
Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to  
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.  
TDI/IN 0  
TCK/IN 3  
TMS/IN 1  
TDO/IN 2  
Input This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin  
to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.  
Input This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the  
Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.  
Input This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for  
the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.  
Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin  
to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.  
IN 4 - IN 7  
GND  
VCC  
Dedicated Input Pins to the device.  
Ground (GND)  
Vcc  
NC1  
No Connect  
I/O  
Input/Output Pins These are the general purpose I/O pins used by the logic array.  
1. NC pins are not to be connected to any active signals, VCC or GND.  
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