Specifications ispLSI 2128E
Functional Block Diagram
Figure 1. ispLSI 2128E Functional Block Diagram
RESET
Input Bus
GOE 0
GOE 1
Output Routing Pool (ORP)
D6
D5
Output Routing Pool (ORP)
D2
D1
D3
Megablock
Generic Logic
IN 5
IN 4
D7
D0
D4
Blocks (GLBs)
I/O 95
I/O 94
I/O 93
I/O 92
C7
C6
I/O 0
I/O 1
I/O 2
I/O 3
A0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 4
I/O 5
I/O 6
I/O 7
I/O 87
I/O 86
I/O 85
I/O 84
A1
C5
C4
I/O 8
I/O 9
I/O 10
I/O 11
I/O 83
I/O 82
I/O 81
I/O 80
A2
A3
Global
Routing
Pool
I/O 12
I/O 13
I/O 14
I/O 15
I/O 79
I/O 78
I/O 77
I/O 76
C3
C2
(GRP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 75
I/O 74
I/O 73
I/O 72
A4
A5
I/O 20
I/O 21
I/O 22
I/O 23
I/O 71
I/O 70
I/O 69
I/O 68
C1
C0
I/O 24
I/O 25
I/O 26
I/O 27
I/O 67
I/O 66
I/O 65
I/O 64
A6
A7
I/O 28
I/O 29
I/O 30
I/O 31
TCK/ IN 0
TMS/IN 1
B0
B1
B2
B5
B6
B7
B3
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
BSCAN
0139/2128E
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise. By
connecting the VCCIO pins to a common 5V or 3.3V
power supply, I/O output levels can be matched to 5V or
3.3V compatible voltages. When connected to a 5V
supply, the I/O pins provide PCI-compatible output drive.
Clocks in the ispLSI 2128E device are selected using the
dedicatedclockpins. Threededicatedclockpins(Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128E device contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBsandallof theinputsfromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
LATTICE [ LATTICE SEMICONDUCTOR ]
