2064VL 参数 Datasheet PDF下载

型号：	2064VL
PDF下载：	下载PDF文件查看货源
内容描述：	2.5V在系统可编程SuperFAST⑩高密度PLD [2.5V In-System Programmable SuperFAST⑩ High Density PLD]
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文件页数/大小：	14 页 / 188 K
品牌：	LATTICE [ LATTICE SEMICONDUCTOR ]

Specifications

ispLSI 2064VL

Functional Block Diagram

Figure 1. ispLSI 2064VL Functional Block Diagram (64-I/O and 32-I/O Versions)

GOE 0

GOE 1

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

I/O 31

I/O 30

I/O 29

I/O 28

Input Bus

Generic Logic

Blocks (GLBs)

I/O 27

I/O 26

I/O 25

I/O 24

Input Bus

Generic Logic

Blocks (GLBs)

Megablock

Output Routing Pool (ORP)

Megablock

Output Routing Pool (ORP)

Input Bus

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

TDI/IN 0

TMS/IN 1

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

TCK/IN 3

TDO/IN 2

Input Bus

I/O 4

I/O 5

I/O 6

I/O 7

TDI/IN 0

TDO/IN 1

Input Bus

I/O 4

I/O 5

I/O 6

I/O 7

Global Routing Pool

(GRP)

I/O 43

I/O 42

I/O 41

I/O 40

Global Routing Pool

(GRP)

Output Routing Pool (ORP)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 47

I/O 46

I/O 45

I/O 44

I/O 0

I/O 1

I/O 2

I/O 3

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

GOE0/IN 3

TMS/IN 2

CLK 0

CLK 1

CLK 2

BSCAN

Input Bus

BSCAN

Input Bus

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

The 64-I/O 2064VL contains 64 I/O cells, while the 32-

I/O version contains 32 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

grammed to be a combinatorial input, output or

bi-directional I/O pin with 3-state control and the output

drivers can source 4 mA or sink 8 mA. Each output can

be programmed independently for fast or slow output

slew rate to minimize overall output switching noise.

Device pins can be safely driven to 3.3V signal levels to

support mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and

two or one ORPs are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 32 or 16 universal I/O cells by

two or one ORPs. Each ispLSI 2064VL device contains

two Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2064VL device are selected using

the dedicated clock pins. Three dedicated clock pins (Y0,

Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock can

be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2064VL are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration is totem-pole

configuration. The open-drain/totem-pole option is se-

lectable through the ispDesignEXPERT software tools.

GOE1/Y0

RESET/Y1

TCK/Y2

0139B/2064VL

CLK 0

CLK 1

CLK 2

0139B/2064VL.32IO

RESET

Output Routing Pool (ORP)

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