Specifications
ispGDX160V/VA
Applications (Continued)
Figure 5. Address Demultiplex/Data Buffering
Designing with the ispGDXV/VA
As mentioned earlier, this architecture satisfies the PRSI
class of applications without restrictions: any I/O pin as a
single input or bidirectional can drive any other I/O pin as
output.
For the case of PDP applications, the designer does have
to take into consideration the limitations on pins that can
be used as control (MUX0, MUX1, OE, CLK) or data
(MUXA-D) inputs. The restrictions on control inputs are
not likely to cause any major design issues because the
input possibilities span 25% of the total pins.
The MUXA-D input partitioning requires that designers
consciously assign pinouts so that MUX inputs are in the
appropriate, disjoint groups. For example, since the
MUXA group includes I/O0-39 (160 I/O device), it is not
possible to use I/O0 and I/O9 in the same MUX function.
As previously discussed, data path functions will be
assigned early in the design process and these restric-
tions are reasonable in order to optimize speed and cost.
XCVR
I/OA
I/OB
MUXed Address Data Bus
Buffered
Data
OEA
OEB
To Memory/
Peripherals
Control Bus
Address
Latch
D
Q
Address
CLK
Figure 6. Data Bus Byte Swapper
D0-7
XCVR
I/OA
I/OB
D0-7
XCVR
I/OA
I/OB
OEA OEB
User Electronic Signature
Data Bus B
Data Bus A
OEA OEB
XCVR
D8-15
I/OA
I/OB
D8-15
XCVR
I/OA
I/OB
OEA OEB
OEA OEB
The ispGDXV/VA Family includes dedicated User Elec-
tronic Signature (UES) E
2
CMOS storage to allow users
to code design-specific information into the devices to
identify particular manufacturing dates, code revisions,
or the like. The UES information is accessible through
the boundary scan programming port via a specific com-
mand. This information can be read even when the
security cell is programmed.
Control Bus
Security
Figure 7. Four-Port Memory Interface
4-to-1
16-Bit MUX
Bidirectional
Port #1
OE1
Port #2
OE2
Port #3
OE3
Bus 2
The ispGDXV/VA Family includes a security feature that
prevents reading the device program once set. Even
when set, it does not inhibit reading the UES or device ID
code. It can be erased only via a device bulk erase.
To
Memory
Memory
Port
OEM
Bus 4
Bus 3
SEL0
Note: All OE and SEL lines driven by external arbiter logic (not shown).
Bus 1
Port #4
OE4
SEL1
7
LATTICE [ LATTICE SEMICONDUCTOR ]
