Specifications
ispLSI 1032/883
ispLSI 1032/883 Timing Model
I/O Cell
GRP
Feedback
Ded. In
GLB
ORP
I/O Cell
#26
I/O Reg Bypass
#20
Input
D Register Q
RST
#21 - 25
GRP 4
#28
GRP
Loading
Delay
#27, 29,
30, 31, 32
4 PT Bypass
#33
20 PT
XOR Delays
#34, 35, 36
#55
D
RST
#38, 39,
40, 41
GLB Reg Bypass
#37
GLB Reg
Delay
Q
ORP Bypass
#46
ORP
Delay
#45
#47
I/O Pin
(Output)
#48, 49
I/O Pin
(Input)
#55
Reset
Clock
Distribution
Y1,2,3
#51, 52,
53, 54
#50
Control RE
PTs
OE
#42, 43, CK
44
Y0
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
iobp +
t
grp4 +
t
ptck(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#20 + #28 + #44
)
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6)
t
h
= Clock (max) + Reg h - Logic
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#20 + #28 + #44
)
+
(
#39
) - (
#20 + #28 + #35
)
5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6)
t
co
= Clock (max) + Reg co + Output
=
(t
iobp +
t
grp4 +
t
ptck(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#20 + #28 + #44
)
+
(
#40
)
+
(
#45 + #47
)
25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0)
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
t
su
= Logic + Reg su - Clock (min)
=
(t
iobp +
t
grp4 +
t
20ptxor
)
+
(t
gsu
) - (t
gy0(min) +
t
gco +
t
gcp(min)
)
=
(
#20 + #28 + #35
)
+
(
#38
) - (
#50 + #40 + #52
)
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3)
t
h
= Clock (max) + Reg h - Logic
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gh
) - (t
iobp +
t
grp4 +
t
20ptxor
)
=
(
#50 + #40 + #52
)
+
(
#39
) - (
#20 + #28 + #35
)
5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6)
t
co
= Clock (max) + Reg co + Output
=
(t
gy0(max) +
t
gco +
t
gcp(max)
)
+
(t
gco
)
+
(t
orp +
t
ob
)
=
(
#50 + #40 + #52
)
+
(
#40
)
+
(
#45 + #47
)
25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0)
1. Calculations are based upon timing specifications for the ispLSI 1032-60.
8
LATTICE [ LATTICE SEMICONDUCTOR ]
