Specifications
ispLSI and pLSI 1032E
Functional Block Diagram
Figure 1. ispLSI and pLSI 1032E Functional Block Diagram
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 7
IN 6
RESET
Input Bus
Generic
Logic Blocks
(GLBs)
D7
D6
Output Routing Pool (ORP)
GOE 1/IN 5
GOE 0/IN 4
D5
D4
D3
D2
D1
D0
C7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*SDI/IN 0
*MODE/IN 1
A0
A1
Output Routing Pool (ORP)
A2
A3
A4
A5
A6
C6
Output Routing Pool (ORP)
C5
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
Global
Routing
Pool
(GRP)
C4
C3
C2
C1
C0
lnput Bus
A7
B0
B1
B2
B3
B4
B5
B6
B7
Clock
Distribution
Network
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Megablock
*ispEN/NC
*SDO/IN 2
*SCLK/IN 3
I/O 16
I/O 17
I/O 18
I/O 19
Input Bus
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
*ISP Control Functions for ispLSI 1032E Only
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
registered input, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
and pLSI 1032E device contains four Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI and pLSI 1032E devices are se-
lected using the Clock Distribution Network. Four
dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into
the distribution network, and five clock outputs (CLK 0,
CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to
route clocks to the GLBs and I/O cells. The Clock Distri-
bution Network can also be driven from a special clock
GLB (C0 on the ispLSI and pLSI 1032E devices). The
logic of this GLB allows the user to create an internal
clock from a combination of internal signals within the
device.
2
I/O 28
I/O 29
I/O 30
I/O 31
Y0
Y1
Y2
Y3
lnput Bus
LATTICE [ LATTICE SEMICONDUCTOR ]
