Specifications ispLSI and pLSI 1032
ispLSI and pLSI 1032 Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#26
I/O Reg Bypass
#20
GRP 4
#28
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47
I/O Pin
(Input)
I/O Pin
(Output)
#48, 49
Input
Register
GRP
Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34, 35, 36
#55
#27, 29,
30, 31, 32
#55
#21 - 25
RST
#38, 39,
40, 41
Reset
Clock
Control
PTs
RE
OE
CK
Distribution
Y1,2,3
Y0
#51, 52,
53, 54
#42, 43,
44
#50
1
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
= (#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #28 + #44) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
1
Derivations of tsu, th and tco from the Clock GLB
tsu
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
tco
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032-80.
8
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
