Specifications ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
-90
-80
-60
5
2
1
TEST
PARAMETER
#
DESCRIPTION
UNITS
COND.
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
–
–
12
17
–
–
–
15
20
–
–
–
20
25
–
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
ns
ns
2
3
4
5
6
7
8
9
pd2
3
Clock Frequency with Internal Feedback
90.9
58.8
125
6
80
50
100
7
60
38
83
9
max (Int.)
max (Ext.)
max (Tog.)
su1
MHz
MHz
MHz
ns
1
Clock Frequency with External Feedback
–
–
–
(
)
tsu2 + tco1
4
Clock Frequency, Max Toggle
–
–
–
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
–
–
8
–
10
–
–
13
–
co1
ns
0
–
0
0
h1
ns
9
–
10
–
–
13
–
–
su2
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
–
10
–
12
–
16
–
co2
ns
0
0
0
h2
ns
–
15
–
–
17
–
–
22.5
–
r1
ns
10
–
10
–
13
–
rw1
ns
14 Input to Output Enable
15
15
–
18
18
–
24
24
–
en
ns
15 Input to Output Disable
–
–
–
dis
ns
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
4
5
6
wh
ns
4
–
5
–
6
–
wl
ns
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2
–
2
–
2.5
8.5
–
su5
ns
6.5
–
6.5
–
–
h5
ns
Table 2-0030-32/90,80,60C
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
5
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
