Specifications
ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
5 2
PARAMETER
TEST
#
COND.
DESCRIPTION
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
(
tsu2
1
tco1
)
+
Clock Frequency, Max Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
-90
12
17
–
–
–
–
8
–
–
–
–
–
–
-80
15
20
–
–
–
–
–
–
–
–
–
–
-60
20
25
–
–
–
–
13
–
–
16
–
22.5
–
24
24
–
–
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN. MAX. MIN. MAX. MIN. MAX.
1
2
3
4
5
6
7
8
9
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1.
2.
3.
4.
5.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
S
S
10
12
17
18
18
–
–
–
–
90.9
58.8
125
6
–
0
9
–
0
–
–
–
4
4
2
6.5
80
50
7
–
0
–
0
–
–
–
5
5
2
6.5
100
60
38
83
9
–
0
13
–
0
–
13
–
–
6
6
2.5
8.5
USE 1032E-80
FOR NEW DESIG
N
10
15
15
15
–
–
–
–
10
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-Bit counter using GRP feedback.
fmax
(Toggle) may be less than 1/(twh +
twl).
This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
USE 1032E-70
FOR NEW DESIG
N
10
10
Table 2-0030-32/90,80,60C
5
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
