Specifications
ispLSI 1024/883
Internal Timing Parameters
1
2
PARAMETER
#
DESCRIPTION
-60
MIN. MAX.
UNITS
Outputs
t
ob
t
oen
t
odis
Clocks
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
47
48
49
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
–
–
–
4.0
6.7
6.7
ns
ns
ns
50
51
52
53
54
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
6.0
4.6
1.3
4.6
1.3
6.0
7.3
6.6
7.3
6.6
ns
ns
ns
ns
ns
Global Reset
t
gr
55
Global Reset to GLB and I/O Registers
–
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
LATTICE [ LATTICE SEMICONDUCTOR ]
