Specifications
ispLSI 1024/883
Internal Timing Parameters
1
PARAMETER
#
2
DESCRIPTION
-60
MIN. MAX.
UNITS
Inputs
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
GRP
t
grp1
t
grp4
t
grp8
t
grp12
t
grp16
t
grp24
GLB
t
4ptbp
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gr
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
20
21
22
23
24
25
26
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
–
–
7.3
1.3
–
–
–
2.7
4.0
–
–
4.0
3.3
5.3
ns
ns
ns
ns
ns
ns
ns
27
28
29
30
31
32
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 24 GLB Loads
–
–
–
–
–
–
2.0
2.7
4.0
5.0
6.0
8.3
ns
ns
ns
ns
ns
ns
33
34
35
36
37
38
39
40
41
42
43
44
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
–
–
–
–
–
1.3
6.0
–
–
–
–
4.6
8.6
9.3
10.6
12.7
1.3
–
–
2.7
3.3
13.3
12.0
9.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
46
ORP Delay
ORP Bypass Delay
–
–
3.3
0.7
ns
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
6
LATTICE [ LATTICE SEMICONDUCTOR ]
