ML145170
LANSDALE Semiconductor, Inc.
CRYSTAL OSCILLATOR CONSIDERATIONS
use of R1 is not necessary in most cases.
To verify that the maximum DC supply voltage does not
cause the crystal to be overdriven, monitor the output frequen-
The following options may be considered to provide a refer-
ence frequency to Lansdale’s/Motorola’s CMOS frequency
synthesizers.
cy at the REF
pin (OSC is not used because loading
out
out
impacts the oscillator). The frequency should increase very
slightly as the DC supply voltage is increased. An overdriven
crystal decreases in frequency or becomes unstable with an
increase in supply voltage. The operating supply voltage must
be reduced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start–up time is proportional to the value of R1.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
DC coupled to OSC . If the oscillator does not have CMOS
in
logic levels on the outputs, capacitive or AC coupling to
Through the process of supplying crystals for use with CMOS
inverters, many crystal manufacturers have developed expertise
in CMOS oscillator design with crystals. Discussions with
such manufacturers can prove very helpful (see Table 2).
OSC may be used (see Figures 8a and 8b).
in
For additional information about TCXOs, visit freescale.com
on the world wide web.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 18.
Figure 18. Pierce Crystal Oscillator Circuit
The crystal should be specified for a loading capacitance
(C ) which does not exceed 20 pF when used at the highest
L
operating frequencies listed in the Loop Specifications table.
Larger C values are possible for lower frequencies. Assuming
L
R1 = 0 Ω, the shunt load capacitance (C ) presented across the
L
C C
out
C1 C2
C1 C2
in
C
C
C
a
stray
L
C
C
out
in
*May be needed in certain cases. See text.
where
Cin = 5.0 pF (see Figure 19)
C
out = 6.0 pF (see Figure 19)
Ca = 1.0 pF (see Figure 19)
C1 and C2 = external capacitors (see Figure 18)
Figure 19. Parasitic Capacitances of the Amplifier
and Cstray
C
stray = the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
crystal can be estimated to be:
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSC and
in
OSC
pins to minimize distortion, stray capacitance, stray
Figure 20. Equivalent Crystal Networks
out
inductance, and startup stabilization time. Circuit stray capaci-
tance can also be handled by adding the appropriate stray value
to the values for C and C . For this approach, the term
in
out
Cstray becomes 0 in the above expression for C .
L
A good design practice is to pick a small value for C1 such
as 5 o 10 pF. Next, C2 is calculated. C1 < C2 results in a more
robust circuit for start–up and is more tolerant of crystal
parameter variations.
Power is dissipated in the effective series resistance of the
crystal R , in Figure 20. The maximum drive level specified by
e
the crystal manufacturer represents the maximum stress that
the crystal can withstand without damage or excessive shift in
operating frequency. R1 in Figure 18 limits the drive level. The
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
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