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KK4043B 参数 Datasheet PDF下载

KK4043B图片预览
型号: KK4043B
PDF下载: 下载PDF文件 查看货源
内容描述: 四三态R / S锁存器高压硅栅CMOS [Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS]
分类和应用: 锁存器高压
文件页数/大小: 6 页 / 395 K
品牌: KODENSHI [ KODENSHI KOREA CORP. ]
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KK4043B  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +20  
-0.5 to VCC +0.5  
-0.5 to VCC +0.5  
±10  
Unit  
V
VCC  
VIN  
VOUT  
IIN  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
V
mA  
mW  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
PD  
Tstg  
TL  
Power Dissipation per Output Transistor  
Storage Temperature  
100  
-65 to +150  
260  
mW  
°C  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SOIC Package)  
°C  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
3.0  
0
Max  
18  
Unit  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
VIN, VOUT  
TA  
VCC  
+125  
V
-55  
°C  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range  
GND(VIN or VOUT)VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
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