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KK4042BN 参数 Datasheet PDF下载

KK4042BN图片预览
型号: KK4042BN
PDF下载: 下载PDF文件 查看货源
内容描述: 四计时獶?闭锁高压硅栅CMOS [Quad Clocked 獶?Latch High-Voltage Silicon-Gate CMOS]
分类和应用: 高压
文件页数/大小: 6 页 / 370 K
品牌: KODENSHI [ KODENSHI KOREA CORP. ]
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KK4042B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200 kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Clock to Q
(Figure 1)
Maximum Propagation Delay, Clock to Q
(Figure 1)
Maximum Propagation Delay, Data to Q
(Figure 2)
Maximum Propagation Delay, Data to Q
(Figure 2)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
450
200
160
500
230
180
220
110
80
300
150
100
200
100
80
Guaranteed Limit
≥-55°C
25°C
450
200
160
500
230
180
220
110
80
300
150
100
200
100
80
7.5
≤125°C
900
400
320
1000
460
360
440
220
160
600
300
200
400
200
160
Unit
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200 kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
w
Parameter
Minimum Pulse Width, Clock (Figure 1)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
200
100
60
50
30
25
120
60
50
Guaranteed Limit
≥-55°C
25°C
200
100
60
50
30
25
120
60
50
Not rise or fall
time sensitive
≤125°C
400
200
120
100
60
50
240
120
100
Unit
ns
t
su
Minimum Setup Time, Data to Clock
(Figure 1)
Minimum Hold Time, Clock to Data
(Figure 1)
Maximum Input Rise or Fall Time, Clock
(Figure 1)
ns
t
h
ns
t
r
, t
f
µs
4