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KK4034BDW 参数 Datasheet PDF下载

KK4034BDW图片预览
型号: KK4034BDW
PDF下载: 下载PDF文件 查看货源
内容描述: 8级静态双向并行/串行输入/输出总线寄存器高压硅栅CMOS [8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silicon-Gate CMOS]
分类和应用: 高压
文件页数/大小: 9 页 / 571 K
品牌: KODENSHI [ KODENSHI KOREA CORP. ]
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KK4034B  
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200k, Input tr=tf=20 ns)  
VCC  
V
Guaranteed Limit  
Symbol  
fmax  
Parameter  
Unit  
-55°C  
25°C  
125°C  
Maximum Clock Frequency (Figure 2)  
5.0  
10  
15  
2
5
7
2
5
7
1
2.5  
3.5  
MHz  
tPHL, tPLH Maximum Propagation Delay, A(B) Parallel  
Data In to B(A) Parallel Data Out; Serial to  
Parallel Data Out (Figures 1,2)  
5.0  
10  
15  
700  
240  
170  
700  
240  
170  
1400  
480  
340  
ns  
ns  
ns  
pF  
tPLZ, tPHZ, Maximum Propagation Delay, A/B or AE to  
tPZL, tPZH “A” Output (Figure 3)  
5.0  
10  
15  
400  
160  
120  
400  
160  
120  
800  
320  
240  
tTHL, tTLH Maximum Output Transition Time, Any Output  
(Figures 1,2)  
5.0  
10  
15  
200  
100  
80  
200  
100  
80  
400  
200  
160  
CIN  
Maximum Input Capacitance  
-
7.5  
TIMING REQUIREMENTS (CL=50pF, RL=200 k, Input tr=tf=20 ns)  
VCC  
Guaranteed Limit  
Symbol  
tsu  
Parameter  
V
Unit  
ns  
-55°C  
25°C  
125°C  
Minimum Setup Time, Serial Data to Clock  
(Figure 4)  
5.0  
10  
15  
160  
60  
40  
160  
60  
40  
320  
120  
80  
tsu  
Minimum Setup Time, Parallel Data to Clock  
(Figure 4)  
5.0  
10  
15  
50  
30  
20  
50  
30  
20  
100  
60  
40  
ns  
ns  
ns  
ns  
ns  
th  
Minimum Hold Time, Clock to Data (Figure 4)  
5.0  
10  
15  
50  
15  
10  
50  
15  
10  
100  
30  
20  
tw  
Minimum Pulse Width, AE, P/S, A/S  
(Figure 5)  
5.0  
10  
15  
350  
140  
80  
350  
140  
80  
700  
280  
160  
tw  
Minimum Pulse Width, Clock (Figure 2)  
5.0  
10  
15  
250  
100  
70  
250  
100  
70  
500  
200  
140  
tr ,tf  
Minimum Input Rise or Fall Time, Clock  
(Figure 2)  
5.0  
10  
15  
15  
15  
15  
15  
15  
15  
30  
30  
30  
4