TECHNICAL DATA
KK4021B
8-Bit Shift Register
High-Voltage Silicon-Gate CMOS
The KK4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-
Serial Converter) with a synchronous Serial Data Input (D
S
), a Clock
Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight
asynchronous Parallel Data Inputs (P
0
-P
7
) and Buffered Parallel Outputs
from the last three stages (Q
5
-Q
7
).
Information on the Parallel Data Inputs (P0-P7) is asynchronously
loaded into the register while the Parallel Load Input (PL) is HIGH,
independent of the Clock (CP) and Serial Data (D
S
) inputs. Data present
in the register is stored on the HIGH-to-LOW transition of the Parallel
Load Input (PL).
When the Parallel Load Input is LOW, data on the Serial Data Input
(D
S
) is shifted into the first register position and all the data in the register
is shifted one position to the right on the LOW-to-HIGH transition of the
Clock Input (CP).
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4021BN Plastic
KK4021BDW SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
SERIAL OPERATION:
t
n
n+1
n+2
n+3
CP
D
S
0
1
0
1
X
PL
0
0
0
0
0
Q
5
t=n+6
0
1
0
1
Q
5
P
7
D
Q
6
t=n+7
0
1
0
Q
6
Q
5
D
Q
6
D
Q
7
t=n+8
0
1
Q
7
Q
7
D
PARALLEL OPERATION:
CP
D
S
PL P
5
P
6
X
PIN 16 =V
CC
PIN 8 = GND
X
1
D
D
X = don’t care
D = 1 or 0
1
KODENSHI [ KODENSHI KOREA CORP. ]
