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KK24LC08 参数 Datasheet PDF下载

KK24LC08图片预览
型号: KK24LC08
PDF下载: 下载PDF文件 查看货源
内容描述: 4K / 8K 2.5V的CMOS串行EEPROM [4K/8K 2.5V CMOS Serial EEPROMs]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 10 页 / 215 K
品牌: KODENSHI [ KODENSHI KOREA CORP. ]
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KK24LC04/08
Figure 3. Bus timing Data
FUNCTIONAL DESCRIPTION
The
KK24LC04/08
supports a bidirectional two wire bus and data transmission protocol. A device
that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The
bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus
access, and generates the START and STOP conditions, while the
KK24LC04/08
works as slave.
Both, master and slave can operate as transmitter or receiver but the master device determines
which mode is activated.
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been defined (see Figure 4).
Bus not Busy (A)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START
condition. All commands must be preceded by a START condition.
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP
condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of the data bytes transferred between the START and STOP conditions is determined by the
master device and is theoretically unlimited, although only the last sixteen will be stored when
doing a write operation. When an overwrite does occur it will replace data in a first in first out
fashion.
4