KK0066
TERMINAL DESCRIPTION
Pin
V
DD
V
SS
V
1
– V
5
SEG1–
SEG40
COM1–
COM16
OSC1
OSC2
CLK1
CLK2
M
Output
Output
Output
Input
Output
Data latch clock
Data shift clock
Alternated signal
for LCD driver
output
Display data
interface
Power
Negative Supply
Voltage
Segment output
Common output
Oscillator
INP/
OUT
Name
Operating Voltage
DESCRIPTION
For logical circuit (+5V
±
10%)
0V(GND)
Bias voltage level for LCD driving
Segment signal output for LCD driving
Common signal output for LCD driving
Both pin connected to Rf resistor or ceramic resonator for
internal oscillator circuit. In case of external frequency
use only, the frequency is input to OSC1 terminal.
Clock output terminal for the serially transferred data to
be latched to the driver.
Clock output terminal used when D terminal data output
shifts the inside of the driver.
The alternating signal to convert LCD drive waveform to
AC.
Character pattern data, which is corresponding to each
common signal, is supplied to driver serially.
High
Low
Selection
Non selection
INTERFACE
Power
Supply
LCD
LCD
Resistor or
Ceramic
Resonator
IZ0065
D
E
R/W
Input
Enable
Read/Write
Start anable signal to read or write the data
R/W signal input is used to select the read/write mode
MPU
High
Low
Read mode
Write mode
RS
Register select
Register selection input
High
Low
Data register
read and write)
(for
Instruction register (for
write), Busy flag, address
counter (for read)
DB
0
–
DB
7
Input/O
utput
Data interface
Used for data transfer between the MPU and KK0066.
These terminals are for data bus with bidirectional
three-state.
Initial 4 bit (DB
0
-DB
3
) are not used during 4 bit
operation (DB
7
can be used as a busy flag)
6
KODENSHI [ KODENSHI KOREA CORP. ]
