SPM0423HD4H-WB
5. INTERFACE CIRCUIT
VDD
VDD
.1f
.1f
SELECT
SELECT
Mic
(High)
Mic
(Low)
DATA CLOCK
Microphone
Mic (High)
Mic (Low)
SELECT
VDD
Asserts DATA On
Rising Clock Edge
Falling Clock Edge
Latch DATA On
Falling Clock Edge
Rising Clock Edge
GND
Note: All Ground pins must be connected to ground.
Capacitors near the microphone should not contain Class 2 dielectrics.
Detailed information on acoustic, mechanical, and system integration can be found in
the latest SiSonicTM Design Guide application note.
6. TIMING DIAGRAM
1/FCLOCK
tEDGE
VIH
VIL
tEDGE
CLOCK
tDZ
tDV
VOH
Mic (High)
Data
High Z
DATA
(SELECT = VDD)
VOL
tDZ
tDV
VOH
DATA
(SELECT = GND)
High Z
Mic (Low)
Data
VOL
Revision: C
2/28/2013
Sheet 6 of 13
©2013 Knowles Electronics
KNOWLES [ KNOWLES ELECTRONICS ]
