26 | Keysight | U4164A Logic Analyzer Module - Data Sheet
Technical Specifications and Characteristics
All specifications refer to the combination of a U4164A logic analyzer module, U4201A logic analyzer probe cable, and any Keysight
Soft Touch probe. Probe variations will influence results.
State (Synchronous) sampling mode
Maximum state data rate Option 02G, 2.5 GHz state mode (spec)
2.5 Gb/s on 136 channels per U4164A, using either or both edges of clock (spec)
4 Gb/s on 68 channels per U4164A, clocking on either edge of the clock (typ)
Maximum state data rate -01G 1.4 GHz state mode (spec)
2.5 Gb/s on 136 channels per U4164A, using both edges of clock (spec)
2.8 Gb/s on 68 channels per U4164A, clocking on either edge of the clock (typ)
Maximum state data rate Option -700
1.4 Gb/s on 136 channels using both edges of clock (spec)
Maximum state data rate 350 MHz standard (base)
Maximum state clock frequency (typ)
700 Mb/s on 136 channels using both edges of clock (spec)
2.5 GHz Option -02G
1.4 GHz Option -01G
700 MHz Option -700
350 MHz standard (base)
12.5 MHz (single edge)
Minimum state clock frequency1 (typ)
6.25 MHz (both edges)
Sample position adjustment resolution (typ)
Sample position adjustment accuracy (typ)
Minimum data valid window (typ)
Minimum setup time (typ)
5 ps or 20 ps
± 150 ps
100 ps
50 ps
Minimum hold time (typ)
50 ps
Minimum eye height (typ)
100 mV
Sample position adjustment range (typ)
Minimum state clock pulse width (typ)
Number of clocks (nom)
7 ns
200 ps
1
Minimum time between active clock edges (typ)
Maximum time between active clock edges 1 (typ)
Number of clock qualifiers
400 ps
80 ns
4 (pods 2, 3, 4, and 5 on clocking module)
Clock qualifier setup time
150 ps
Clock qualifier hold time
150 ps
Number of “RESET” clock qualifiers
“RESET” clock qualifier setup time
“RESET” clock qualifier hold time
Time tag resolution (typ)
1 (pod 7 of clocking module)
2 ns
0 ps
80 ps
66 days
Maximum time count between stored states (typ)
1. Clock can pause for up to 66 days once every 8 or more edges.
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