04 | Keysight | N5399C, N5399D HDMI Electrical Performance Validation and Compliance Software - Data Sheet
HDMI 2.0: What is Different from HDMI 1.4?
The high definition multimedia interface
Testing HDMI transmitters
HDMI is a 19-pin interface (see Figure 1) that is favored in the
industry for the transmission of digital video to high resolution
displays. To accomplish this, four high-speed differential lanes
are used: one that serves as a clock (Ck) and three others (D0,
D1, D2) for the pixel data. These four lanes are referred to as
the TMDS lanes (transition minimized differential signaling). The
data lanes are encoded with an 8b/10b overlay that minimizes
the transitions (different from the ANSII 8b/10b, which seeks
to maximize the transitions). The TMDS system makes use of a
divided forwarded clock, which is referred to as the ‘TMDS clock.’
For HDMI 2.0, the divisor is 40 while the divisor is 10 for HDMI
1.4b and earlier. Prior to HDMI 2.0, the maximum composite bit
rate was 10.2 Gbs (three data lanes at 3.4 Gbs per lane); now with
HDMI 2.0, the maximum composite bit rate has been increased to
17.8 Gbs (three data lanes at 5.94 Gbs).
To test a digital transmitter of any sort, the test equipment must
be connected to an interface. The interface is usually not a
coaxial design, so it is imperative that a test point access adapter
(TPA) that breaks out the test signals to a coaxial design is used.
TPAs you can use with the Keysight HDMI compliance software
are presented in Table 3c. An illustration of how HDMI signals
are accessed by the measurement system is shown in Figure 3.
It is not commonly the case that all HDMI TMDS signals can be
connected to the measurement system at the same time, so the
test process will likely include reconnection of signals, which the
software will guide you through.
TP1’
TP1
ACQ
Oscilloscope
channels
Connecting
network
to
Transmitter
Sink (Display)
TP1
TP2
Oscilloscope
Data Tx
Data Rx
Test point adapter
Device
under test
Channel (Cable)
xN
PLL
xN
PLL
Figure 3. Test point adapter breaking out signals to the oscilloscope
through cable network.
Ck frequency = Data rate/N
HDMI 1.4: N=10
Ck
HDMI 2.0: N=40
In HDMI, there are tests that measure single-ended parameters
as well as differential parameters. When single-ended
Hot plug detect
+5
Utility
SDA
SCL
parameters are being measured, the waveform for a single line
of the differential lane is being analyzed – for example, D0+. If
this single line is compared with another line such as D0- (as
in intra-pair skew testing), then the D0- signal will be routed
to one oscilloscope channel and the D0+ will be routed to
another. If a differential test is being performed, then the two
single-ended signals are subtracted from one another in the
oscilloscope (performing a Math function, for instance), and the
resultant waveform is analyzed for the parameter of interest
(level, rise time, etc.). There are times when two differential
signals (two TMDS lanes) are required (data eye test being the
most significant case). When performing such tests, the HDMI
EPVC software can use single-ended acquisitions or can acquire
the information from differentially probed lines. In all cases, the
connecting network, shown in Figure 3, and the oscilloscope
connection must behave according to the topology requirements
shown in Figure 2 for the HDMI sink connection.
CEC
EDID
Controller
CEC
DDC GND
Figure 1. HDMI Interface.
AVcc
TMDS topology
RT
RT
Cable
HDMI sink
D+
D–
ITMDS
HDMI transmitter
Figure 2. Differential lane topology of transition minimized differ-ential
signaling used in HDMI. (Originally from specification 1.3.)
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