21 | Keysight | N5393D PCI Express® 3.0 (Gen3) Software for Infiniium Oscilloscopes - Data Sheet
Tests Performed
The PCI Express electrical performance
Assertion no.
Description
Keysight PCI
Express
SigTest
validation and compliance software
performs the following tests as per
the PCI Express 1.0a and 1.1 electrical
specifications for add-in cards and
motherboard systems as documented
in Section 4 of the base specification
(“PHY”) and Section 4 of the card
electromechanical specification (“EM”).
For reference, the tests performed by the
SigTest application are also noted.
Transmitter tests
PHY.3.1#26
PHY.3.2#1
DC common mode voltage
De-emphasis on multiple bits same polarity in
succession
Transition bit voltage
Transmitter eye diagram
Unit interval without SSC variations
Minimum D+/D- output rise/fall time
Jitter median to max deviation
Maximum RMS AC common mode voltage
Minimum eye width
Y
Y
N
N
PHY.3.2#2
PHY.3.3#1
PHY.3.3#2
PHY.3.3#3
PHY.3.3#4
PHY.3.3#5
PHY.3.3#9
Receiver tests
PHY.3.4#1
PHY.3.4#2
PHY.3.4#6
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
For Gen2 testing coverage, the
PCI-SIG decided not to create checklist,
as was done for Gen1. For test coverage
refer to section 4.7.2. Table 4-8 of the
PCI Express 2.0 Card Electromechanical
Specification.
Minimum receiver eye diagram
AC peak common mode input voltage
Jitter median to max deviation input
Y 1
Y 1
Y 1
N
N
N
System board (connector) tests
EM.4#4
EM.4#20
Minimum jitter
Transmitter path eye diagram
Y
Y
Y
Y
For PCI Express 3.0, test coverage
includes items listed on table 4-18 under
section 4.3.3 of the PCI Express 3.0 Base
Specification.
Reference clock (connector) tests
PHY.3.3#2
PHY.3.3#1
PHY.3.3#1
PHY.3.3#4
PHY.3.3#4
PHY.3.3#9
PHY.3.2#2
Phase jitter
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Average clock period
Duty cycle
Y
Y
Y
Y
Y
Y
Y
N/A 1
N/A
N/A
N/A
N/A
N/A
N/A
Add-in card (connector) tests
EM.4#13
EM.4#19
Minimum jitter
Transmitter path eye diagram
Y
Y
Y
Y
1. Receiver tests provided by the Keysight PCI Express software are listed under the PCIe 1.x or 2.0 test tabs
do not validate the receiver’s tolerance or ability to correctly receive data. They validate the signal at the
receiver against specified tolerances.
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