16 | Keysight | N5393D PCI Express® 3.0 (Gen3) Software for Infiniium Oscilloscopes - Data Sheet
Reference Clock Measurements
The PCI Express 1.0a specification
failed to specify the input bandwidth
the reference clock receiver or phase
jitter of the reference clock itself. This is
important because jitter that lies within
the loop bandwidth the receiver PLL for
the reference clock will transfer onto the
high speed data lines. This hole in the PCI
Express specification was corrected in the
1.1 update.
InfiniiMax 1169A probe with
E2678A socket adapter
attached to CLB
Note 2pF capacitors added
to CLB to create REFCLK
compliance load as per spec
The N5393D includes powerful reference
clock evaluation tools including phase
jitter. The PCIe 1.1 specification calls
for a very specific phase jitter filter that
focuses the measurement on the jitter that
lies between 1.5 and 22-MHz. The filter
also amplifies the jitter 3 dB (peaking)
within this region. The Keysight N5393D
includes proprietary filtering software
(patent pending) that exactly implements
the filters specified in the PCI Express
specification. The N5393D also includes
reference clock tests based on the PCIe
2.0 and 3.0 specification.
Figure 22. The N5393D software includes important tests for the reference clock of your
PCI Express system. This signal can be probed using the Keysight InfiniiMax 1169A probes in
conjunction with the PCI-SIG’s compliance load board.
Utilizing Keysight’s InfiniiMax 1169A high
performance differential probes, or direct
cabled connections, you can measure
your reference clock using the PCI-SIG’s
Compliance Load Board or custom test
fixture.
Reference clock test connection using CLB2
– Reference clock tests
– Phase jitter
– Rising edge rate
– Falling edge rate
– Differential input high voltage
– Differential input low voltage
– Average clock period
– Duty cycle
Figure 23. This shows the CLB2 inserted into the CBB2 test fixture, representing the setup required
to test add-in cards.
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