10 | Keysight | N4960A Serial BERT 17 and 32 Gb/s - Data Sheet
Spread spectrum clock
(N4960A-CJ1 serial BERT
controller)
Large library of common stress patterns
The N4960A serial BERT controller comes with a library of stress patterns including
PRBS, divided clock, JSPAT, JTSPAT, K28 series, and CJ series for optical telecom and
datacom testing.
The main synthesizer in the N4960A-CJ1
serial BERT controller can be modulated
to enable spread spectrum clocking (SSC).
Spread spectrum clocking is not gener-
ally considered to be a stress, but rather
a method of controlling electromagnetic
interference (EMI), by spreading the peak
energy of the system clock over a broad
portion of the spectrum. In practice, SSC
modulates the system clock in the device
with a large phase deviation at a relatively
low frequency, generally 30 or 33 kHz.
The modulation wave shape is usually a
triangle wave, to keep the power spec-
trum even over the modulation band. SSC
is included in clock synthesizers used in
BERTs to emulate a transmitter from a de-
vice which employs SSC. To assure proper
tracking of the BERT or sampling scope
testing a device with SSC, all three clock
outputs of the N4960A-CJ1 (jittered,
delayed and divided) are modulated with
the same SSC signal. The SSC deviation
range is 0 to 1% (1% = 10,000 ppm). The
modulation envelope is a triangle wave-
form. The modulation frequency can be
set from 1 Hz to 50 kHz. In addition, there
are three settings for deviation direction:
down, center, and up (relative to the clock
frequency setting).
Jitter tolerance testing
Keysight provides an affordable solution for testing jitter tolerance. The N4980A
multi-instrument BERT software saves you time and money by providing a way to effi-
ciently test jitter tolerance.
The optional JTOL measurement package (N4980A-JTS) performs jitter tolerance
compliance and characterization. Setup is quick and easy using the jitter tolerance
setup panel.
Figure 15. Jitter tolerance setup panel in N4980A.
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