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M9393A-UK6 参数 Datasheet PDF下载

M9393A-UK6图片预览
型号: M9393A-UK6
PDF下载: 下载PDF文件 查看货源
内容描述: [M9393A PXIe Performance Vector Signal Analyzer]
分类和应用:
文件页数/大小: 39 页 / 3429 K
品牌: KEYSIGHT [ Keysight Technologies ]
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18 | Keysight | M9393A PXIe Performance Vector Signal Analyzer – Data Sheet  
Technical Specifications and Characteristics  
Standard Configuration - Options F08, F14, F18, F27  
Time and acquisition  
Maximum capture memory 47  
Option M01  
Memory size  
512 MB  
2 GB  
Non-list mode acquisition limit  
128 MSample  
List mode acquisition limit  
64 MSample  
Option M05  
512 MSample  
256 MSample  
Option M10  
4 GB  
1 GSample  
512 MSample 48  
Segments  
Minimum length  
32 bytes  
Maximum length  
Full capture memory 49  
Maximum sample rate  
Option B04 / 40 MHz  
Option B10 / 100 MHz  
Option B16 / 160 MHz  
List mode  
Specification  
50 MS/s complex, 100 MS/s real  
125 MS/s complex, 250 MS/s real  
200 MS/s complex, 400 MS/s real  
Maximum number of segments  
Trigger sources  
3201  
External, magnitude, wideband magnitude, wideband burst, software, immediate  
Per acquisition  
Trigger modes  
Triggering  
Delay range 50  
−0.1 to +1 s  
1 sample  
2 ns  
Delay resolution  
Delay accuracy  
Holdoff range  
0 to 1 s  
Holdoff resolution  
Acquisition minimum size  
Acquisition maximum size  
Timing 51  
10 ns  
2 samples  
1 GSamples  
Channel-to-channel synchronization  
≤ ± 1 ns, nominal  
Repeatability across instrument state changes  
< 50 ps, nominal  
47. Sample count is based on 32-bit samples. For 64-bit samples, divide by 2.  
48. The maximum size for a single list point capture is limited to 512 MSamples (2 GB). However, with option M10, total capture of  
up to 3.999 GB is available across all list mode captures.  
49. The user can allocate memory for one or more acquisitions. Each acquisition takes up the memory that needs to be a power of 2.  
Minimum is 32 bytes.  
50 Negative trigger delay limited to capture size.  
51. Configured with a Keysight M9018A PXIe chassis for up to 4 channels. Repeatability across power cycles, IVI sessions, and module slot changes.  
Chassis FPGA version 1.05 or greater required.  
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