17 | Keysight | M8195A 65 GSa/s Arbitrary Waveform Generator and M8197A Multi-Channel Synchronization Module - Data Sheet
Timing characteristics
The sequencing of a single M8195A can be controlled with the ‘Trigger/Gate Input’ as well as the ‘Event Input’ of the M8195A. In a
synchronous system that consists of one M8197A and up to four M8195A, the sequencing of the entire synchronous system can be
controlled with the ‘Trigger/Gate Input’ as well as the ‘Event Input’ of the M8197A. A single M8195A or a synchronous system can
operate asynchronously or synchronously. In case of synchronous operation, a timing requirement between the Reference Clock Output
and ‘Trigger/Gate Input’ or ‘Event Input’ must be met.
M8195A
M8197A
Delay
Trigger/Gate Input to Data Out
40192 sample clock cycles + 0 ns (nom)
40192 sample clock cycles + 0.15 ns (nom)
45317 sample clock cycles + 8 ns (nom)
45317 sample clock cycles + 8 ns (nom)
Event Input to Data Out
Delay accuracy, asynchronous operation
Trigger/Gate Input to Data Out
Event Input to Data Out
± 100 ps (typ)
± 100 ps (typ)
± 20 ps (typ)
± 100 ps (typ)
Delay accuracy, synchronous operation
Trigger/Gate Input to Data Out
Event Input to Data Out
± 1 ps (typ)
± 1 ps (typ)
± 1 ps (typ)
± 1 ps (typ)
Synchronous operation
Set-up time
-2.5 ns (typ) (‘TRIG IN’, ‘EVENT IN’ to rising edge -1.9 ns (typ) (‘TRIG IN’, ‘EVENT IN’ to rising edge
of ‘REF CLK OUT’)
of ‘REF CLK OUT’)
Hold time
5.1 ns (typ) (Rising edge of ‘REF CLK OUT’ to
‘TRIG IN’, ‘EVENT IN’)
4.5 ns (typ) (Rising edge of ‘REF CLK OUT’ to
‘TRIG IN’, ‘EVENT IN’)
Skew between normal and complement
Skew between any pair of outputs
within one M8195A module
0 ps ± 1 ps (nom)
0 ps ± 5 ps (typ) 1
across multiple M8195A modules
0 ps ± 100 ps (typ) 2
1. can be adjusted to 0 ps using variable channel delay
2. can be adjusted to 0 ps using variable module delay and variable channel delay.
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