13 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
M3302A-C22
Parameter
Min
Typ
Max
Units
Comments
General specifications
Analog output jitter
AWG trigger to output jitter
< 2
< 2
ps
ps
RMS (cycle-to-cycle)
RMS (cycle-to-cycle) for any trigger referenced to the chassis clock;
independent of input trigger jitter if input jitter < 4nS peak-to-peak
Trigger resolution
10
< 20
< 50
< 150
< 2
ns
Channel-to-channel skew
ps
Between ch 0 & ch 1, and ch 2 & ch 3
Between any channel
Between modules, chassis dependant2
ps
ps
Clock output jitter
Clock accuracy and stability
AC specifications
Spurious-free dynamic range (SFDR)
fout = 10 MHz
ps
RMS (cycle-to-cycle)
PXIe, cPCIe versions; chassis dependent1.
100
ppm
Pout = 4 dBm, measured from DC to max frequency
70
64
65
63
dBc
dBc
dBc
dBc
fout = 80 MHz
fout = 120 MHz
fout = 160 MHz
Crosstalk (adjacent channels)
fout = 10 MHz
< –105
–75
dB
dB
dB
dB
fout = 80 MHz
fout = 120 MHz
–88
fout = 160 MHz
–73
Crosstalk (non-adjacent channels)
fout = 10 MHz
< –105
–78
dB
dB
dB
dB
fout = 80 MHz
fout = 120 MHz
< –105
–92
fout = 160 MHz
Phase noise (SSB)
offset = 1 KHz
< –127
< –133
< –138
< –145
dBc/Hz
dBc/Hz
dBc/Hz
dBm/Hz
offset = 10 KHz
offset = 100 KHz
Average noise power density
1. This value corresponds to a M9505A chassis. This value can be improved with an external chassis clock or a system timing module.
2. This value corresponds to a M9005A PXIe chassis.
Table 10. AC performance
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