12 | Keysight | M3300A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
M3300A-C24
Typ
M3300A-C48
Typ
Parameter
Min
Max
Min
Max Units
Comments
General characteristics
Analog output jitter
AWG trigger to output jitter
<2
<2
<2
<2
ps
ps
RMS (cycle-to-cycle)
RMS (cycle-to-cycle) for any trigger
referenced to the chassis clock;
independent of input trigger jitter if input
jitter < 4nS peak-to-peak
Trigger resolution
10
10
ns
Channel-to-channel skew
<20
<50
150
<2
<20
<50
150
<2
ps
Between ch 0 & ch 1, and ch 2 & ch 3
Between any channel
Between modules, chassis dependant 2
ps
ps
Clock output jitter
ps
RMS (cycle-to-cycle)
Clock accuracy and stability
AC characteristics
25
25
ppm
PXIe, cPCIe versions; chassis dependent1.
Spurious-free dynamic range (SFDR)
Pout = 4 dBm, measured from DC to max
frequency
fout = 10 MHz
fout = 80 MHz
68
64
57
54
68
64
57
54
dBc
dBc
dBc
dBc
fout = 120 MHz
fout = 160 MHz
Crosstalk (adjacent channels)
fout = 10 MHz
<–105
–85
–75
<–105
–85
–75
dB
dB
dB
dB
dB
dB
fout = 40 MHz
fout = 80 MHz
fout = 120 MHz
–88
–73
–88
–73
fout = 160 MHz
fout = 200 MHz
–85
–85
Crosstalk (non-adjacent channels)
fout = 10 MHz
<–105
–86
<–105
–86
dB
dB
dB
dB
dB
dB
fout = 40 MHz
fout = 80 MHz
–78
–78
fout = 120 MHz
<–105
–92
<–105
–92
fout = 160 MHz
fout = 200 MHz
–100
–100
Phase noise (SSB)
offset = 1 KHz
<–127
<–133
<–138
<–142
<–127
<–133
<–138
<–142
dBc/Hz
dBc/Hz
dBc/Hz
dBm/Hz
offset = 10 KHz
offset = 100 KHz
Average noise power density
1. This value corresponds to a M9505A chassis. This value can be improved with an external chassis clock or a system timing module.
2. This value corresponds to a M9005A PXIe chassis.
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