12 | Keysight | M3202A PXIe Arbitrary Waveform Generator with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
M3202A-CH2
Typ
M3202A-CH4
Typ
Parameter
Min
Max
Min
Max
Units
Comments
General characteristics
Analog output jitter
AWG trigger to output jitter
<2
<2
<2
<2
ps
ps
RMS (cycle-to-cycle)
RMS (cycle-to-cycle) for any trigger
referenced to the chassis clock; indepen-
dent of input trigger jitter if input jitter <
4nS peak-to-peak
Trigger resolution
10
<20
<50
<150
<2
10
<20
<50
<150
<2
ns
Channel-to-channel skew
ps
Between ch 0 & ch 1, and ch 2 & ch 3
Between any channel
Between modules, chassis dependent2
ps
ps
Clock output jitter
ps
RMS (cycle-to-cycle)
Clock accuracy and stability
AC characteristics
100
100
ppm
PXIe, cPXIe versions; chassis dependent1
Spurious-free dynamic range (SFDR)
Pout = 0 dBm, measured from DC to max
frequency
fout = 10 MHz
fout = 40 MHz
68
66
62
58
54
53
55
58
68
66
62
58
54
53
55
58
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fout = 80 MHz
fout = 120 MHz
fout = 160 MHz
fout = 200 MHz
fout = 320 MHz
fout = 390 MHz
Crosstalk (adjacent channels)
fout = 10 MHz
<–105
–85
–80
–89
–76
<–105
–85
–80
–89
–76
dB
dB
dB
dB
dB
dB
dB
fout = 40 MHz
fout = 80 MHz
fout = 120 MHz
fout = 160 MHz
fout = 200 MHz
fout = 320 MHz
Crosstalk (non-adjacent channels)
fout = 10 MHz
–86
–83
–86
–83
<–105
–89
<–105
–89
dB
dB
dB
dB
dB
dB
dB
fout = 40 MHz
fout = 80 MHz
–81
–81
fout = 120 MHz
fout = 160 MHz
fout = 200 MHz
fout = 320 MHz
–103
–95
–103
–95
–102
–97
–102
–97
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