04 | Keysight | M3100A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional Block Diagram
Channel 1
Channel 1
output
Channel x
Input settings
Full scale, Z,
coupling (as
available)
Prescaler
÷
Data
acquisition
(DAQx)
Channel x
output
Analog
trigger
Channel n
Channel n
output
Figure 1. M3100A input functional block diagram, all channels have identical input structure
Ordering Information 1
Product
Description
M3100A
PXIe digitizer: 100 MSa/s, 14 Bits
Options
Description
M3100A-CH4 / -CH8
M3100A-CLF
Four channels 2 / eight channels
Fixed sampling clock, low jitter 2
M3100A-M01 / -M12 / -M20
HW programming options
M3100A-HVI
Memory 16 MB, 8 MSamples 2 / 128 MB, 60 MSamples / 2 GB, 1 GSamples
Description
Enabled HVI programming, requires an HVI design environment license (M3601A)
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
M3100A-FP1
M3100A-K32 / -K41
Related software
M3601A
Description
HVI design environment
FPGA design environment
M3602A
1. All options must be selected at time of purchase and are not upgradable
2. These options represent the standard configuration