IRFR320, IRFU320, SiHFR320, SiHFU320
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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KERSEMI [ Kersemi Electronic Co., Ltd. ]
