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T494A684M035AS 参数 Datasheet PDF下载

T494A684M035AS图片预览
型号: T494A684M035AS
PDF下载: 下载PDF文件 查看货源
内容描述: 固体钽电容器芯片的饭店( T494系列 - 低ESR ,工业级) [SOLID TANTALUM CHIP CAPACITORS
(T494 SERIES - Low ESR, Industrial Grade)]
分类和应用: 电容器钽电容器
文件页数/大小: 48 页 / 1466 K
品牌: KEMET [ KEMET CORPORATION ]
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ADSP-218xN Series  
Program Memory  
Program Memory (Host Mode) allows access to all internal  
memory. External overlay access is limited by a single exter-  
nal address line (A0). External program execution is not  
available in host mode due to a restricted data bus that is  
only 16 bits wide.  
Program Memory (Full Memory Mode) is a 24-bit-wide  
space for storing both instruction opcodes and data. The  
ADSP-218xN series has up to 48K words of Program  
Memory RAM on chip, and the capability of accessing up  
to two 8K external memory overlay spaces, using the exter-  
nal data bus.  
Table 8. PMOVLAY Bits  
Processor  
PMOVLAY  
Memory  
A13  
A12–0  
ADSP-2184N No Internal  
Overlay Region  
Not Applicable  
Not Applicable  
Not Applicable  
ADSP-2185N  
ADSP-2186N No Internal  
Overlay Region  
0
Internal Overlay  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
ADSP-2187N 0, 4, 5  
ADSP-2188N 0, 4, 5, 6, 7  
ADSP-2189N 0, 4, 5  
Internal Overlay  
Internal Overlay  
Internal Overlay  
External Overlay 1  
Not Applicable  
Not Applicable  
Not Applicable  
0
Not Applicable  
Not Applicable  
Not Applicable  
13 LSBs of Address Between 0x2000 and  
0x3FFF  
All Processors  
1
All Processors  
2
External Overlay 2  
1
13 LSBs of Address Between 0x2000 and  
0x3FFF  
Data Memory  
plete in one cycle. Accesses to external memory are timed  
using the wait states specified by the DWAIT register and  
the wait state mode bit.  
Data Memory (Full Memory Mode) is a 16-bit-wide space  
used for the storage of data variables and for memory-  
mapped control registers. The ADSP-218xN series has up  
to 56K words of Data Memory RAM on-chip. Part of this  
space is used by 32 memory-mapped registers. Support also  
exists for up to two 8K external memory overlay spaces  
through the external data bus. All internal accesses com-  
Data Memory (Host Mode) allows access to all internal  
memory. External overlay access is limited by a single exter-  
nal address line (A0).  
Table 9. DMOVLAY Bits  
Processor  
DMOVLAY  
Memory  
A13  
A12–0  
ADSP-2184N No Internal Overlay  
Region  
Not Applicable  
Not Applicable  
Not Applicable  
ADSP-2185N  
ADSP-2186N No Internal Overlay  
Region  
0
Internal Overlay  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
ADSP-2187N 0, 4, 5  
ADSP-2188N 0, 4, 5, 6, 7, 8  
ADSP-2189N 0, 4, 5, 6, 7  
Internal Overlay  
Internal Overlay  
Internal Overlay  
External Overlay 1  
Not Applicable  
Not Applicable  
Not Applicable  
0
Not Applicable  
Not Applicable  
Not Applicable  
13 LSBs of Address  
Between 0x0000  
and 0x1FFF  
All Processors  
1
All Processors  
2
External Overlay 2  
1
13 LSBs of Address  
Between 0x0000  
and 0x1FFF  
–14–  
REV. 0