IT6605
Pin Description
Digital Video Onput Pins
Pin Name
QE[35:0]
Direction Description
Type
Pin No.
1-3, 7-10, 13-16,
108-111, 114-117,
120-123, 126-129,
132-135, 138-141,
144
Output
Digital Video Output Pins. Channel swap and
MSB-LSB reversal are supported through register
setting.
LVTTL
PCLK
Output
Output data clock. The backend controller should
use the rising edge of PCLK to strobe QE[35:0]
Data enable
LVTTL
5
DE
Output
Output
Output
Output
LVTTL
LVTTL
LVTTL
LVTTL
19
20
21
22
HSYNC
VSYNC
EVENODD
Horizontal sync. signal
Vertical sync. signal
Indicates whether the current field is Even or Odd
for interlaced format
Digital Audio Onput Pins
Pin Name
XTALIN
Direction Description
Type
Pin No.
95
Input
Crystal clock input (for Audio PLL)
Crystal clock output (for Audio PLL)
Audio master clock
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
XTALOUT
MCLK
Output
Output
Output
Output
94
89
SCK_DCLK
WS_DR0
I2S serial clock output, doubles as DSD clock
86
I2S word select output, doubles as DSD Serial Right CH0 data
85
output
I2S0_DL0
I2S1_DR1
I2S2_DL1
I2S3_DR2
SPDIF_DL2
Output
Output
Output
Output
Output
I2S serial data output, doubles as DSD Serial Left CH0 data
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
81
82
83
84
78
output
I2S serial data output, doubles as DSD Serial Right CH1 data
output
I2S serial data output, doubles as DSD Serial Left CH1 data
output
I2S serial data output, doubles as DSD Serial Right CH2 data
output
S/PDIF audio output, doubles as DSD Serial Left CH2 data
output
MUTE_DR3 Output
Mute output, doubles as DSD Serial Right CH3 data output
DSD Serial Left CH3 data output
LVTTL
LVTTL
75
77
DSD_DL3
Output
Feb-2012 Rev:0.92 5/38
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