IT6605
Video AC Timing Specification
Under functional operation conditions
Symbol
Tpixel
Parameter
PCLK pixel clock period1
Conditions
Min.
4.44
Typ
Max
40
Unit
ns
Single-edged
clocking
Fpixel
TCDE
FCDE
TPDUTY
TPH
PCLK pixel clock frequency1
PCLK dual-edged clock period2
PCLK dual-edged clock frequency2
PCLK clock duty cycle
25
8.88
25
225
40
MHz
ns
Dual-edged clocking
112.5
60%
0.4
MHz
40%
0
PCLK rising edge to Transition time4
Single-pixel mode
ns
Notes:
1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency
should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding
pixel frequencies.
2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i.
3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user
through register programming.
4. The PCLK rising edge to transition time could be got when Vclk_inv (reg[0x1D]bit[4]=‘0’) is disabled. If user
intends to delay 0.5Tpixel for TTL data output, please enable Vclk_inv bit (reg[0x1D]bit[4]=‘1’). And then TPH will
increase 0.5Tpixel.
PCLK rising edge to transition time under single-pixel mode
Feb-2012 Rev:0.92 18/38
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