IT6605
Major video processings in the IT6605 are carried out in 14 bits per channel in order to minimize
rounding errors and other computational residuals that occur during processing. General description
of video processing blocks is as follows:
HDCP engine (HDCP)
The HDCP engine decrypts in incoming data. Preprogrammed HDCP keys are embedded in the
IT6605. Users need not worry about the purchasing and management of the HDCP keys as Chip
Advanced Technology will take care of them.
Upsampling (YCbCr422 to YCbCr444)
In cases where input HDMI video data are in YCbCr 4:2:2 format and output is selected as 4:4:4, this
block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible
artifacts generated during upsampling.
Bi-directional Color Space Conversion (YCbCr ↔ RGB)
Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order
to offer full compatibility between various Source and Sink combination, this block offers bi-directional
RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the matrix coefficients
of the CSC engine in the IT6605 are fully programmable. Users could elect to employ their preferred
conversion formula.
Downsampling (YCbCr444 to YCbCr422)
In cases where input HDMI video data are in YCbCr 4:4:4 format and output is selected as YCbCr
4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid
visible artifacts generated during downsampling.
Dithering (Dithering 12-to-10 or 12-to-8)
For outputing to the 10-bits / 8-bits-per-channel formats, decimation might be required depending on
the exact input formats. This block performs the necessary dithering for decimation to prevent visible
artifacts from appearing.
Supported output Video Formats
Table 1 lists the output video formats supported by the IT6605. The listed Output Pixel Clock
Frequency in MHz is the actual clock frequency at the output pin PCLK, regardless of the color depth.
According to the HDMI Specification v1.3, the input TMDS clock frequency could be 1.25 times or 1.5
times that of the output PCLK frequency, depending on the color depth:
For 24-bit inputs, TMDS Clock frequency = 1 x PCLK frequency
For 30-bit inputs, TMDS Clock frequency = 1.25 x PCLK frequency
For 36-bit inputs, TMDS Clock frequency = 1.5 x PCLK frequency
The IT6605 also provides automatic video mode detection. The system controller can elect to check
out respective status registers to get the informations.
Feb-2012 Rev:0.92 10/38
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ITE [ ITE TECH.INC. ]
