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IS61WV51216BLL-10TLI-TR 参数 Datasheet PDF下载

IS61WV51216BLL-10TLI-TR图片预览
型号: IS61WV51216BLL-10TLI-TR
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 512KX16, 10ns, CMOS, PDSO44, LEAD FREE, PLASTIC, TSOP2-44]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 20 页 / 199 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS61WV51216ALL  
IS61WV51216BLL  
IS64WV51216BLL  
512K x 16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH 3.3V SUPPLY  
OCTOBER2009  
FEATURES  
• High-speed access times:  
8, 10, 20 ns  
• High-performance, low-power CMOS process  
• Multiple center power and ground pins for greater  
noise immunity  
DESCRIPTION  
The ISSI IS61WV51216ALL/BLL and IS64WV51216BLL  
are high-speed, 8M-bit static RAMs organized as 512K  
words by 16 bits. It is fabricated using ISSI's high-perform-  
anceCMOStechnology.Thishighlyreliableprocesscoupled  
withinnovativecircuitdesigntechniques,yieldshigh-perfor-  
mance and low power consumption devices.  
• Easy memory expansion with CE and OE op-  
tions  
CE power-down  
• Fully static operation: no clock or refresh  
required  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down with CMOS input levels.  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE. The active LOW  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
• TTL compatible inputs and outputs  
• Single power supply  
VDD 1.65V to 2.2V (IS61WV51216ALL)  
speed = 20ns for VDD 1.65V to 2.2V  
VDD 2.4V to 3.6V (IS61/64WV51216BLL)  
speed = 10ns for VDD 2.4V to 3.6V  
speed = 8ns for VDD 3.3V + 5%  
• Packages available:  
The device is packaged in the JEDEC standard 44-pin  
TSOP Type II and 48-pin Mini BGA (9mm x 11mm).  
48-ball miniBGA (9mm x 11mm)  
– 44-pin TSOP (Type II)  
• Industrial and Automotive Temperature Support  
• Lead-free available  
• Data control for upper and lower bytes  
FUNCTIONAL BLOCK DIAGRAM  
512K x 16  
MEMORY ARRAY  
A0-A18  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. F  
10/01/09