IC61C1024
IC61C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled,
OE
is HIGH or LOW)
(1 )
t
WC
ADDRESS
VALID ADDRESS
t
SA
CE
t
SCE
t
HA
WE
t
AW
t
PWE1
t
PWE2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
D
IN
t
HD
DATA
IN
VALID
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle)
(1,2)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
CE
LOW
t
AW
t
PWE1
WE
t
SA
D
OUT
DATA UNDEFINED
t
HZWE
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
9
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
