IS42S81600D, IS42S16800D
An example is shown in WRITE to WRITE diagram. Data n
+ 1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITEcommand.Full-speedrandomwriteaccesseswithin
a page can be performed to the same bank, as shown in
Random WRITE Cycles, or each subsequent WRITE may
be performed to a different bank.
WRITES
WRITE bursts are initiated with a WRITE command, as
showninWRITECommanddiagram.
WRITE COMMAND
CLK
HIGH
CKE
Data for any WRITE burst may be truncated with a subse-
quentREADcommand, anddataforafixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ com mand is registered, the
data inputs will be ignored, and WRITEs will not be ex-
ecuted. An example is shown in WRITE to READ. Data n +
1 is either the last of a burst of two or the last desired of a
longerburst.
CS
RAS
CAS
WE
Dataforafixed-lengthWRITEburstmaybefollowed by,or
truncatedwith,aPRECHARGEcommandtothesamebank
(providedthatautoprechargewasnotactivated),andafull-
page WRITE burst may be truncated with a PRECHARGE
commandtothesamebank.ThePRECHARGEcommand
should be issued tDPL after the clock edge at which the last
desiredinputdataelementisregistered.Theautoprecharge
mode requires a tDPL of at least one clock plus time,
regardless of frequency. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask input
datafortheclockedgepriorto,andtheclockedgecoincident
with,thePRECHARGEcommand.Anexampleisshowninthe
WRITEtoPRECHARGEdiagram.Datan+1iseitherthelast
ofaburstoftwoorthelastdesiredofalongerburst.Following
thePRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until tRP is met.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A9
A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Note: A9 is "Don't Care" for x16.
The starting column and bank addresses are provided with
theWRITEcommand,andautoprechargeiseitherenabled
ordisabledforthataccess. Ifautoprechargeisenabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
In the case of a fixed-length burst being executed to comple-
tion,aPRECHARGEcommandissuedattheoptimumtime(as
describedabove)providesthesameoperationthatwouldresult
from the same fixed-length burst with auto precharge. The
disadvantageofthePRECHARGEcommandisthatitrequires
that the command and address buses be available at the
appropriatetimetoissuethecommand;theadvantageofthe
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
During WRITE bursts, the first valid data-in element will be
registeredcoincidentwiththeWRITEcommand. Subsequent
dataelementswillberegisteredoneachsuccessivepositive
clockedge.Uponcompletionofafixed-lengthburst,assum-
ing no other commands have been initiated, the DQs will
remain High-Z and any additional input data will be ignored
(see WRITE Burst). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0
andcontinue.)
Fixed-length or full-page WRITE bursts can be truncated
withtheBURSTTERMINATEcommand.Whentruncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
datawritten(providedthatDQMisLOWatthattime)willbe
the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data n is the last desired data element
of a longer burst.
Data for any WRITE burst may be truncated with a subse-
quent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any
clock following the previous WRITE command, and the data
providedcoincidentwiththenewcommandappliestothenew
command.
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
