IS42S16400F
IC42S16400F
ꢀ 8.ꢀCONCURRENTꢀAUTOꢀPRECHARGE:ꢀBankꢀnꢀwillꢀinitiateꢀtheꢀAUTOꢀPRECHARGEꢀcommandꢀwhenꢀitsꢀburstꢀhasꢀbeenꢀinter-
ruptedꢀbyꢀbankꢀm’sꢀburst.
ꢀ 9.ꢀBurstꢀinꢀbankꢀnꢀcontinuesꢀasꢀinitiated.
ꢀ10.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlaterꢀ(ConsecutiveꢀREADꢀBursts).
ꢀ11.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀREADꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(READꢀtoꢀWRITE).ꢀDQMꢀshouldꢀbeꢀusedꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀ
prevent bus contention.
ꢀ12.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀREAD),ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀlastꢀvalidꢀWRITEꢀ
toꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ13.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀWRITE).ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀ
clockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ14.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀtheꢀ
READꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ
1).
ꢀ15.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀ
TheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ2).
ꢀ16.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀ
after tWR is met, where tw r ꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregis-
teredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀmꢀ(FigꢀCAPꢀ3).
ꢀ17.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtw r ꢀisꢀmet,ꢀwhereꢀtꢀWRꢀbeginsꢀwhenꢀtheꢀ
WRITEꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀtoꢀbankꢀmꢀ
(FigꢀCAPꢀ4).
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
